Power-saving means is widely used to minimize power consumption in a computer system. Many kinds and levels of power-saving modes are developed to achieve the purpose. One of the examples is so-called as ACPI. ACPI (Advanced Configuration and Power Management Interface) is a specification defining standard interfaces for hardware configuration and power management of the power-saving means. According to the ACPI specification, the central processing unit (CPU) of the computer system operates in various power states, e.g. C1, C2, C3, etc. Different power states result in different levels of power saving effects. For any power-saving mechanism, it is important to reduce power consumption while providing a stable operational environment for circuit at a relatively low temperature.
Generally speaking, the power management for the CPU of the computer system is implemented with the south bridge chip of the chipset. Referring to a conventional computer scheme of FIG. 1, for activating and deactivating power-saving modes, the south bridge chip 2 includes a stop clock control module 20 coupled to the CPU 1 and north bridge chip 3, and an interrupt control device 22 coupled to the stop clock control module 20 and one or more peripheral equipment, e.g. peripheral device 4.
When the operating system (OS) of the computer system is to enter a power-saving state, the CPU 1 asserts a sleep command to the south bridge chip 2. In response to the sleep command, the stop clock control module 20 of the south bridge chip 2 asserts a stop clock signal STPCLK# to the CPU 1 via a clock signal pin 21. Once the STPCLK# signal is generated, the CPU 1 asserts a stop grant signal STPGNT to the south bridge chip 2 via the north bridge chip 3 through data buses connecting thereto. In response to the STPGNT signal, the CPU 1, as well as the entire computer system, enters the power-saving state so as to reduce power consumption.
Afterwards, the CPU 1 can be awaked when interrupted by any of the peripheral devices. For example, in response to the receipt of an interrupt signal asserted by the peripheral device 4 via the interrupt signal pin 40, the interrupt control device 22 of the south bridge chip 2 issues a wake-up signal to trigger the stop clock control module 20 of the south bridge chip 2 to de-assert the STPCLK# signal. Thus, the CPU 1 and the entire computer system are awaked to recover to the normal operation state.
With the increasing number and variety of peripheral devices and promotion of computer performance, new and diverse architectures of computer systems have been developed. For example, the computer system may involve a plurality of input/output advanced programmable interrupt controllers (10 APICs). Particularly, as shown in FIG. 2, peripheral equipment such as peripheral device 6 can be connected to the north bridge chip 3 other than the south bridge chip 2, and respective 10 APICs 25 and 50 are arranged in the south bridge chip 2 and north bridge chip 3. The peripheral device 6 is communicable with the north bridge chip 3 via a PCI (peripheral component interconnect)-to-PCI bridge device 5, and the IO APIC 50 is disposed in the PCI-to-PCI bridge device 5. When the interruption is asserted by the peripheral device 4 connected to the south bridge chip 2 during the power-saving period, the STPGNT signal can be de-asserted via the clock signal pin 21 connected between the south bridge chip 2 and the CPU 1, as mentioned above. The PCI-to-PCI bridge device 5 where the IO APIC 50 is disposed, however, is not coupled to stop clock control module 20 as the IO APIC 25 does. Therefore, the CPU 1 or the computer system cannot be effectively awaked by the peripheral device 6 from the power-saving state to the normal operation state.